1. Field
Exemplary embodiments of the present invention relate to a non-volatile memory device and a method for fabricating the same, and more particularly, to a non-volatile memory device with a three-dimensional structure, in which a plurality of memory cells are vertically stacked on a substrate, and a method for fabricating the same.
2. Description of the Related Art
A non-volatile memory device refers to a memory device which is capable of maintaining stored data without a power supply. A variety of non-volatile memory devices, such as flash memories have been extensively used.
Meanwhile, as higher integration of a memory device having a two-dimensional structure, in which memory cells are formed as a single layer on a silicon substrate, has reached physical limits, there is being developed a non-volatile memory device having a three-dimensional structure, in which a plurality of memory cells are vertically stacked on a silicon substrate. In more detail, a non-volatile memory device with a three-dimensional structure includes pillar-shaped channels protruding upward from a substrate and a plurality of interlayer dielectric layers and a plurality of gate electrode layers alternately stacked while surrounding the pillar-shaped channels.
In such a structure, in order to apply a power supply to each gate electrode layer, the ends of the plurality of interlayer dielectric layers and the plurality of gate electrode layers alternately stacked are formed in a stepped shape by an etching process, and contacts are formed at the ends of the respective gate electrode layers.
However, since the etching process is performed by forming a photoresist pattern on the plurality of interlayer dielectric layers and the plurality of gate electrode layers alternately stacked and etching the stacked structure even though the width of the photoresist pattern, i.e., an etching mask, decreases, the process is difficult to achieve. For example, an initially used photoresist pattern is to be very thick and the stacked structure is likely to be damaged in the etching process.
Moreover, the contact forming process may not be properly performed because the heights of the respective gate electrode layers are different from one another. For example, when forming contact holes for exposing the ends of the gate electrode layers, the gate electrode layer at the top may be perforated due to a long exposure to etching gas, but the gate electrode layer at the bottom may not be exposed.